Conventional flash memory systems, otherwise known as flash electrically erasable programmable read only memories (FLASH EEPROMs), typically include a two-dimensional array of floating gate memory transistors, or "cells," formed on a semiconductor substrate. These cells are arranged into strings, known as NAND strings, to form bit lines, wherein each cell is coupled to the next cell in the string by coupling the source of one transistor to the drain of another transistor. Word lines, disposed perpendicularly to the bit lines, connect to the control gate of one transistor in each NAND string.
Initially, the cells in a flash memory are erased so that the floating gate memory transistors have a certain threshold voltage, such as -2V. Selected cells are programmed to a higher threshold voltage by applying a high voltage, such as 18V-23V, for a period of time, such as about 200 .mu.s, to the word lines of the selected cells. This voltage is typically controlled through a high voltage transistor on the periphery of the memory device. Flash memory devices are attractive in application environments requiring more frequent programming than an EPROM but needing to be updated less often than typical main memory, cache, or registers (i.e., DRAM or SRAM).
Therefore, operation of a NAND flash memory requires a high voltage transistor that can reliably support occasional voltages up to 23V. Referring to FIG. 5, a high-voltage transistor used in a flash memory device is formed on a substrate 500 and electrically isolated by isolation structures 502, which may be formed by Local Oxidation of Silicon (LOCOS), trench isolation, or other such techniques. The high-voltage transistor includes a doped source region 504 and a doped drain region 506 separated by a channel region 508. A gate oxide 510 is formed over the channel region 508 to insulate the gate electrode 510 from the channel region 508. The high voltage transistor also includes a source electrode 514 and a drain electrode 516, coupled to the source region 504 and the drain region 506 respectively.
The high voltage across the transistor, however, causes a grave concern for the reliability of the transistor. A common failure scenario for a field effect transistor is a breakdown in the gate oxide 510 of the transistor, usually involving carriers injected into the gate oxide 510. An important carrier-injection mechanism is a cold carrier injection phenomenon known as Fowler-Norheim tunneling, which is more pronounced for higher gate voltages and thinner gate oxides.
Consequently, a conventional approach for determining the reliability of a transistor is to stress gate oxides of varying thicknesses under direct current (DC) conditions and project the gate oxide reliability for an industry standard ten-year lifetime. Specifically, test structures including transistors with several thin gate oxides, respectively, are manufactured, and subjected to a DC voltage until the transistors break down. The time to breakdown for the device with the thin gate oxides is measured, and the gate oxide thickness for a ten-year lifetime is extrapolated from the respective breakdown times. By this reliability criterion, the oxide thickness sufficient to meet the ten-year lifetime under the DC stress conditions is selected as the minimum gate oxide thickness for the transistor. This approach typically results in gate oxide 510 thicknesses of about 400-500 .ANG. being chosen.
From a performance point of view, however, a thinner gate oxide is preferred if the reliability concerns can be met. For example, a thinner gate oxide results in an increased drive current, which improves switching speed. As another example, a thinner gate oxide leads to a shallower junction depth, providing greater control over short channel effects affecting the threshold voltage (V.sub.T) of the transistor. For yet another example, a thinner gate oxide fosters a smaller gate delay and, hence, faster device performance.